Hi


how to test this 10/100 emac core with hardware..
how to set the Ip address to source and destination in this core?

can anybody help me....


Thanks & Regards
Surendra

Hi All,

I am trying to test the core via the sample project provided @ http://whoyouvotefor.info/ethernet.html
So far my progress has been quite limited.
I am trying synthesise the project for Spartan 3E-1600 ( Diligent ) on ISE 11.1 and after some previous error resolutions ( some with help from the authors ), am getting an error that my be familiar to some of the more experience users. If so please let us know how could I resolve the issue.
"ERROR:Xls:2033 - Port IB of Input buffer infrastructure_top0/DIFF_ENDED_CLKS_INST.SYS_CLK_INST is connected to GND"
The error comes from a file vlog_bl2cl25_top0_infrastructure_top.v generated by Xilinx CoreGen system ( I can attach the file if needed ). The is used as part of the ethmac module for the memory interface generated via MIG 3.0 for storing the Ethernet packets.

Any help is highly appreciated.

Regards,

Stoytcho

The error seems to be due to some kind resolution issue in the Xilinx projects. I am working with ISE 11.1.
Solved my problem by reading http://forums.xilinx.com/xlnx/board/message?board.id=DEENBD&message.id=912&jump=true#M912 explanation and applying it to my specific case.
Basically create a custom .tcl file ( I used the one created by the generation of MIG 3.0 IP core ) and put all your verilog and vhdl source files in it. Run run create_ise.bat ( again in my case crated by the generation of MIG 3.0 IP core). The project synthesizes without any problem.

Regards,

Stoytcho